Recent content by dttprofessor

The soc tile of NVLs is the type of new n100?

Which node they use for NVL soc tile ? 3?18a? Which connection for the separated IMC ？

LPE back to soc tile ?

How about NVL-h？

It's LPE.

DMR have SMT.

All companies in the ARM industry chain, except for ARM itself and chip foundries, have no moat!

The frequency of discussion about chips that have not yet entered QS is completely rumor. The frequency of discussion about chips that have not yet entered QS is completely rumor.

When a 300mm chip was only worth $5,000, the chip factory was just a laborer. Now the price of 300mm chips is already $30,000, and the next generation is moving towards $50,000. Fabless will be the labor force in the next 10 years. When a 300mm chip was only worth $5,000, the chip factory was...

same tile with ptl?

foundry is more huge!

是的

PTL will upgrade foveros-s to 25um ?

I think foveros(36UM@MTL & ARL) makes the higher latency(70ns to ARL-S)，the speed for D2D(3.2GHZ @arl-S) is too slow ,and avoid more heat. Nova lake put the imc @ soc tile too!!! Intel should find the better connection for chip2chip，maybe hybrid bonding ?

4P+4LPE & 2P+4LPE is the same tile ? All PTL mobile use only one socket ?