Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[igor_kavinski]

Because AMD is executing better. Intel has been in brain drain state since 2010.

Intel arguably has a lot more talented people. They are just commandeered by morons who give them impossible and nonsensical things to do. Telling your engineers to copy AMD's chiplet strategy in one fell swoop was bound to fail. Multiple people on these forums raised such concerns when Intel announced the tile architecture of Meteor Lake.

AMD got there gradually, essentially creating beta silicon that worked better than Intel's stagnant Skylake++ architecture for a few years and gave them the head start they needed to execute better with Zen 3 and later architectures. Intel slept the whole time, suddenly woke up from its irresponsible slumber and decided it was going to beat AMD at its own game? This is how we got the Arrow Lake mess.

Panther Lake will tell us if Nova Lake will be any good. Can't wait to see if Intel has learned anything good from their tile misadventures.

 

[DavidC1]

Intel arguably has a lot more talented people. They are just commandeered by morons who give them impossible and nonsensical things to do. Telling your engineers to copy AMD's chiplet strategy in one fell swoop was bound to fail. Multiple people on these forums raised such concerns when Intel announced the tile architecture of Meteor Lake.

They were under morons for nearly 2 decades now. But back then they had talent that made it work despite the troubles.

If they ever do a Core 2 style comeback with the mont team and also succeed with future processes, I would still be wary unless they do a true restructuring away from the finance company they are now. Because if they don't fix the fundamentals, they will be in trouble again.

 

[511]

Intel's GM is just under 40%. To get it to 50% they will have to improve their products significantly, or be under the illusion they are profitable such as under BK management only to cripple themselves afterwards after the bubble pops.

Oftentimes some companies make a product for one-off, just to end up continuing it or even become a focus because the success is beyond their expectations. They aren't in control of GMs - it's nearly entirely up to the market to decide.

So it still baffles me why the CEO would repeat such an obvious thing. Because saying they'll execute better and make better products is indirectly saying their revenue, thus their profits, thus their Gross Margins will rise. This doesn't inspire confidence in Lip-Bu Tan's management.

I still don't know what he plans to do except for cutting middle management which he is already doing.

Craig Barrett - "Copy Exactly"
Paul Otellini - "Tick Tock"
Pat Gelsinger - "5N4Y"
Lip-Bu Tan - "50% GM"

Copy Exactly and Tick Tock are good models tbh especially Copy Exactly which allowed their fab to dominate.

He's trying to do the best he can with what he's got to work with. Although clearing up the middle management mess will remove a lot of unneeded cruft in the operation of the company, the main issue is that the development heads are still the same. The guys with weird ideas like

"HT is bad"

"hybrid architecture is the definitive way forward"

"must only stick to tile architecture" despite not much success with it so far

"AVX-512 matters only in workstation/server markets"

"high speed RAM is better than larger L3 cache" etc.

while AMD does all of those things with much success.

HT is bad or good good depends on the implementation their Implementation kind of sucks so it's better to get rid of it.

Hybrid is definitely the way forward doesn't Zen6 also has LP-E cores 🙂

They were stupid to kill AVX-512 In client due to things not being properly planned.

AMD doesn't have to deal with Fabs that takes so much pressure off of them their success is partly due to TSMC has well.

 

[DavidC1]

I don't know what the heck happened with Gelsinger, because his reputation as a leader in previous companies were stellar. Maybe he wasn't ideal since he became leaders of software corporations.

Also there's a possibility that there are limits to his ability and being an Intel CEO was too much. IBM marketer that got fired after getting promoted to managerial position because she was so good at it comes to mind. In her case, not being promoted would have helped the company. Firing her rather than putting her back into what she was good at was not just an idiotic move, but a braindead one.

Makes me think if him staying as CTO would have been perfect.

Keller did really good in other companies, but failed to do so at Intel. Whatever bureaucratic layers and problems were festering at Intel is making it almost impossible to fix.

 

[coercitiv]

Also there's a possibility that there are limits to his ability and being an Intel CEO was too much.

There's also a distinct possibility that his reign was doomed from the start, no matter the person in charge. Intel's top and middle people would resist and sabotage the required changes until the company was in ruin. (I suspect even their board was in denial)

One analogy comes to mind, and it's not about cars During a press interview, a dermatologist said something that stuck with me: his ideal patient is the one who has already gone to 1-2 other dermatologists for the same issue, because of two reasons related to this medicine field:

• with some skin related issues it takes time to find the proper cure, some amount of trial and error may be required and people often lack the patience and discipline to go through the process with a single doctor. If you're the second or third, you can rely on previous treatment attempts to find the one that works better (and fast)
• in some cases, the body adapts over time and/or the treatment scheme produces results after repeated use, so the second/third doctor has higher chance of success even with the same approach

I hope Lip-Bu Tan was given a mandate for a different Intel - one that is more willing to accept change, though admittedly in a much degraded shape. He's had time to watch the patient resist previous treatment schemes, so he knows what to expect.

 

[jpiniero]

I don't know what the heck happened with Gelsinger, because his reputation as a leader in previous companies were stellar. Maybe he wasn't ideal since he became leaders of software corporations.

Server isn't fixable without the products being at TSMC because it'd simply not be competitive enough otherwise.

Which would be the end of the foundry.

 

[511]

Server isn't fixable without the products being at TSMC because it'd simply not be competitive enough otherwise.

Which would be the end of the foundry.

This is something else Intel design is not being held back by foundry as of now it is held back by their bad Designs look at B580 the perf/mm2 sucks outright even after using TSMC. If anything IFS is the crown Jewel of Intel which they destroyed and are trying to get back on track.

 

[Doug S]

Copy Exactly and Tick Tock are good models tbh especially Copy Exactly which allowed their fab to dominate.

I never could understand why they bragged about "copy exactly". That would be one of the few things one could say with 100% confidence that both engineers and beancounters would suggest as the only reasonable policy.

 

[jpiniero]

I never could understand why they bragged about "copy exactly". That would be one of the few things one could say with 100% confidence that both engineers and beancounters would suggest as the only reasonable policy.

Because that wasn't the policy initially.

 

[511]

Intel's architecture and node planning became weird due to fab delays but it still kind of follows Tick Tock Model.
10nm -> Palm cove was supposed to be shrunk Skylake
10nm+ -> Sunny Cove
10nm++ -> Willow Cove(Sunny Cove+)
10nm+++ aka Intel 7 -> Golden Cove
Intel 4 -> Redwood Cove(GLC+)
N3B -> Lion Cove
18A -> Cougar Cove (Lion Cove +)
18AP/N2 -> Panther Cove

 

[coercitiv]

Intel's architecture and node planning became weird due to fab delays but it still kind of follows Tick Tock Model.

To me this looks less about tick-tock and more about which IP they have available for a given node. They even tried to give it a new name.

MTL is a tock and a shrink - the change to tiles is huge. LNL completely re-imagines the internal structure of an Intel mobile CPU, even if the core themselves are close to previous IP. ARL is a tock and a shrink. There is no rule anymore, no pattern.

 

[DavidC1]

To me this looks less about tick-tock and more about which IP they have available for a given node. They even tried to give it a new name.

I pretty much disregarded that. BK management brought that up, with no effect. It was probably brought up since they were forced to do it because of terrible management. Tick Tock and Copy Exactly actually had real plans.

I never could understand why they bragged about "copy exactly". That would be one of the few things one could say with 100% confidence that both engineers and beancounters would suggest as the only reasonable policy.

Company-wide policy is different from just few sections thinking about it.

 

[511]

@igor_kavinski since you have been craving P cores here is fun little benchmark i found for Skymont vs LNC -7W -3 FPS. intel should release a handheld with 8 Darkmont and 10-12 Xe3 Cores.

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[DavidC1]

@igor_kavinski since you have been craving P cores here is fun little benchmark i found for Skymont vs LNC -7W -3 FPS. intel should release a handheld with 8 Darkmont and 10-12 Xe3 Cores.

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m.weibo.cn

Skymont has GREAT dynamic range. They can make it very performant like with Arrowlake, or very low power as with Lunarlake. It was something Gracemont wasn't able to do, as it only fulfilled the higher performance part. Tremont only got the low power part right.

 

[dttprofessor]

@igor_kavinski since you have been craving P cores here is fun little benchmark i found for Skymont vs LNC -7W -3 FPS. intel should release a handheld with 8 Darkmont and 10-12 Xe3 Cores.

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View attachment 125201
View attachment 125200

It's LPE.

 

[511]

It's LPE.

Yes but it's still skymont

Skymont has GREAT dynamic range. They can make it very performant like with Arrowlake, or very low power as with Lunarlake. It was something Gracemont wasn't able to do, as it only fulfilled the higher performance part. Tremont only got the low power part right.

Yup it's a great core it just needs few improvement to replace P cores.

 

[eek2121]

To me this looks less about tick-tock and more about which IP they have available for a given node. They even tried to give it a new name.

MTL is a tock and a shrink - the change to tiles is huge. LNL completely re-imagines the internal structure of an Intel mobile CPU, even if the core themselves are close to previous IP. ARL is a tock and a shrink. There is no rule anymore, no pattern.

If they went back to tick-tock and moved to a unified core, they would most likely regain performance leadership.

Maybe they could alternate internal/external foundries or something.

 

[LightningZ71]

If they are sticking with a tiled architecture, they could easily regain performance by splitting the e cores and p cores onto different tiles. The P core tile could be optimized then for absolute maximum performance while the e core tile could be optimized for maximum density and efficiency. They would be able to cram more e cores onto a dedicated, high density tile to help with throughput, and they could achieve even higher clocks on the P cores on their own tile.

 

[511]

If they are sticking with a tiled architecture, they could easily regain performance by splitting the e cores and p cores onto different tiles. The P core tile could be optimized then for absolute maximum performance while the e core tile could be optimized for maximum density and efficiency. They would be able to cram more e cores onto a dedicated, high density tile to help with throughput, and they could achieve even higher clocks on the P cores on their own tile.

NVL Tile is 8+16 though 2 P core share L2 this time and 4E cores shares the L2.

 

[dttprofessor]

NVL Tile is 8+16 though 2 P core share L2 this time and 4E cores shares the L2.

How about NVL-h？

 

[511]

How about NVL-h？

Same as PTL-H

 

[Joe NYC]

If they are sticking with a tiled architecture, they could easily regain performance by splitting the e cores and p cores onto different tiles. The P core tile could be optimized then for absolute maximum performance while the e core tile could be optimized for maximum density and efficiency. They would be able to cram more e cores onto a dedicated, high density tile to help with throughput, and they could achieve even higher clocks on the P cores on their own tile.

That would lead to 3-4+ separate CPU dies...

Since Intel is apparently targeting both TSMC N2 and Intel 18A, it would take additional design resources. Which, who know if Intel will still have available...

 

[511]

That would lead to 3-4+ separate CPU dies...

Since Intel is apparently targeting both TSMC N2 and Intel 18A, it would take additional design resources. Which, who know if Intel will still have available...

Everything is finalized for NVL at this point there are only 4 tiles
8+16/8+16 bLLC
4+8/4+0

 

[MS_AT]

2 P core share L2

Is there more evidence for that, or is this based on that recent leak from a while ago? As this makes little, sense conceptually. Unless they will rename cache L1,5 or what it was called, to L2, old L2 will be L3, and the LLC will be L4. On the other hand, if they really want to go forward with this, I hope Intel kept engineers supporting Linux/Windows kernel development, they will need them

 

[511]

Is there more evidence for that, or is this based on that recent leak from a while ago? As this makes little, sense conceptually. Unless they will rename cache L1,5 or what it was called, to L2, old L2 will be L3, and the LLC will be L4. On the other hand, if they really want to go forward with this, I hope Intel kept engineers supporting Linux/Windows kernel development, they will need them

Well you are free to believe it but this is what I have heard from someone reliable.
We can the soul of Kepler_L2 just to be sure . 🙂